Intel Tremont

2019: Technical details about architecture of Tremont

The Intel corporation shared on October 25, 2019 the first technical details about architecture of Tremont – the latest x86 architecture for systems with low power consumption which is designed to provide a considerable gain of performance in comparison with the previous generations.

The architecture of Tremont is the most advanced x86 architecture with low power consumption. We focused on a number of difficult modern workloads, at the same time considered job requirements with network, client applications, the browser and also requirements to the accumulator that allowed us to increase performance actually in all directions. It is the processor architecture of a world class designed to increase the computing power of systems in the compact body with low energy consumption", – Stephen Robinson, the chief engineer on architecture of Tremont in Intel says.

Being the representative of the next generation of x86 microarchitecture with low power consumption, the architecture of Intel Tremont includes a number of improvements in an instruction repertory structure (ISA, instruction set architecture), microarchitecture, security and power management. According to developers, it shows a considerable gain in number of the commands executed for a cycle (IPC, instructions per cycle), in comparison with x86 architecture of Intel for systems with low power consumption of the previous generations. Processors based on Tremont are designed to increase computing power in the compact systems with low power consumption and will allow to create the next generation of the innovation form factors for client devices, new applications for Internet of Things (IoT), effective solutions for data processing centers and other products.

Using technology of volume configuration Intel Foveros, the architecture of Tremont is integrated into broader set of silicon IP blocks in Lakefield that will allow to develop the advanced innovation devices, such as recently announced tablet with two Microsoft Surface Neo screens.

The decoder used in Tremont with support of extraordinary (out-of-order decoder) decoding 6 wide (2 clusters on 3) commands at the beginning of a konveer (front-end) provides more effective transfer of instructions in blocks of execution of a konveer (back end) that is the major factor for ensuring high performance, emphasized in Intel.

As explained in corporation, high-performance architecture are the cornerstone of chips for collecting and data processing. Solutions with low power consumption are necessary for implementation of scenarios of use in more compact form factors.