S-RAM

The main lack of SRAM is extremely low density. As a result at the big physical sizes it has extremely low capacity. Besides use of transistors instead of condensers and their cluster placement considerably increases the device price. For these reasons in RS use only the small amount of SRAM which is used as a cache memory. During the work of SRAM reads data directly from slower dynamic RAM. The efficiency of a cache memory is defined by the number of successful addresses of the processor to it. And as high-speed performance of SRAM is comparable to high-speed performance of the processor, the controller of a cache can foresee requirements of the processor and previously load necessary data. So if the processor obtained information from a cache, such address is considered successful. If it did not occur, then the processor should address DRAM and in this case he should wait a little. Duration of a cycle of modern processors does not exceed 4 nanoseconds, and the speed of RAM reaches 60 nanoseconds. As a result deceleration can be so notable as if the processor has clock rate 16 MHz.

To increase efficiency of all system modern computers are equipped with two types of a cache memory. The cache memory of the first level (L1), or an internal cache, is built in the processor. The cache memory of the second level (L2) long time was set on the motherboard near the connector of the processor and worked at one with it to frequency. Since Pentium Pro the cache memory of the second level though is out of a processor crystal, nevertheless is its part and is mounted in one with it the body. And in the latest models, the cache memory of the second level as well as the first, is a part of a chip of the processor and works at its frequency, half or thirds.