UCIe (Universal Chiplet Interconnect Express)

2022: Presentation of UFCe

On March 3, 2022, it became known that Advanced Semiconductor Engineering, Inc. (ASE), AMD, Arm, Google Cloud, Intel Corporation, Meta, Microsoft, Qualcomm, Samsung and Taiwan Semiconductor Manufacturing Company presented an open standard for chiplets (chiplet) UCIe (Universal Chipset's Open Specification Formation) and UCIe (Universal^[1] Open Specification Development, Interconnect]

Chiplets allow you to create combined hybrid integrated circuits (multi-chip modules), formed from independent semiconductor blocks that are not tied to one manufacturer and interact with each other using a standard high-speed UCIe interface.

To develop a specialized solution, for example, creating a processor with an integrated accelerator for machine learning or processing network operations, it is enough to use existing chiplets with processor cores or accelerators offered by different manufacturers when using UFCe. If there are no standard solutions, you can create your own chip with the necessary functionality, using convenient technologies and solutions.

After that, it is enough to combine the selected chiplets using a block layout in the style of LEGO designers (the proposed technology is somewhat reminiscent of the use of PCIe boards to build a computer filling, but only at the integrated circuit level). Data exchange and interaction between chiplets is carried out using the high-speed UCIe interface, and the paradigm "system-on-package" (SoP, system-on-chip) is used instead of "system-on-chip" (SoC, system-on-chip) for building blocks.

Compared to SoC, the technology of chiplets makes it possible to create replaceable and reusable semiconductor blocks that can be used in different devices, which significantly reduces the cost of developing chips. In chiplet-based systems, different architectures and manufacturing processes can be combined - since each chiplet functions separately, interacting through standard interfaces, blocks with different instruction set architectures (ISAs) such as RISC-V, ARM and x86 can be combined in one product. The use of chiplets also simplifies testing - each chiplet can be tested separately at the stage before integration into the finished Leaders^[2].

Of the interfaces for connecting chiplets, support for PCIe (PCI Express) and CXL (Compute Express Link) is announced.

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